Semiconductor device yield prediction system and method

ABSTRACT

An average fault ratio is calculated from product characteristics of a product as a target of yield prediction, in order to predict yield accurately in the course of manufacturing the prediction target product. 
     With respect to a reference product, whose wiring pattern is different from the prediction target product but manufactured by the same manufacturing process, a monthly electric fault density is calculated from actually measured data. Respective average fault ratios are obtained from product characteristics of the prediction target product and the reference product. A monthly electric fault density of the prediction target product is obtained by multiplying the monthly electric fault density of the reference product by the ratio of the average fault ratios. The yield is calculated by using the monthly electric fault density of the month in which a yield prediction target lot of the prediction target product was processed.

BACKGROUND OF THE INVENTION

The present invention relates to a technique of predicting yields of anelectronic device such as a semiconductor integrated circuit at the timewhen an order for the product is received and at the time when theproduct is manufactured, and particularly to a technique of predictingyields of a semi-custom IC from which kinds of electronic devices can beproduced by connecting circuit elements (macro-cells) depending onrequests of customers.

Generally, a manufacturing process of an electronic device representedby a semiconductor integrated circuit can be broadly divided into apre-process in which a plurality of chips are produced by stackinglayers, such as circuit pattern layers, on a silicon wafer, and apost-process in which the silicon wafer is cut into individual chips tocomplete a product. Most defects generated in the course ofmanufacturing are generated in the pre-process. Accordingly, improvementin yield in the pre-process holds the key to electronic device business.Here, the yield in the pre-process means a rate of good chips determinedby electrical inspection (probing test) as the final test in thepre-process. In other words, the yield in the pre-process means a ratioof the number of good chips to the number of all chips on a wafer.

Manufacturing of an electronic device whose circuit elements(macro-cells) are connected depending on requests of customers issmall-volume production with large variety. Accordingly, to be sure ofmaking a profit, it is necessary to predict yield of a product preciselyand to decide a price properly at the time of receiving an order. In thecase where it is found after the launch of a product that the yield islower than the predicted value, then delivery to the customer is delayedsince no substitute product exists. On the other hand, in the case wherethe yield is higher than the predicted value and surplus articles areproduced, then those articles go to waste since there is a limitednumber of customers requiring the product. Thus, precise prediction ofyield at the time of receiving an order of a product and at the time ofmanufacturing the product is essential to making a profit.

Failures as a cause of deterioration of yield of a pre-process can bebroadly classified into functional failure and characteristic failure. Afunctional failure is a failure as a result of which a circuit does notoperate normally, and arises mainly from breaking or shorting of acircuit pattern, which is caused in turn by a dust particle or a patterndefect occurring in the course of manufacturing. On the other hand, acharacteristic failure is a defect as a result of which performance suchas operating speed of a transistor or a capacitance of a condenser doesnot satisfy design specifications, and arises from slight variations inprocessing: for example, a variation in circuit dimension or oxide filmthickness. Hereinafter in the present description, both dust particlesand pattern defects, which become causes of functional failures, arereferred to as a defect or defects.

As a simulation method for finding degree of functional failures causedby a defect, the Critical Area Analysis is a representative one. This isa method in which degree of occurrence of functional failures iscalculated using a designed circuit pattern and a relation between thetotal number of defects generated and diameter of the defects. Forexample, PDF Solutions, Inc., USA, Defect and Yield Management (DYM),Inc., USA, and HPL, Inc., USA commercialize simulation software usingthe Critical Area Analysis.

Further, a yield prediction method using the Critical Area Analysisobtains an average fault ratio (probability that a defect creates afault) by using a curve of POF (probability of failure) against defectdiameter, which is made by inputting circuit pattern design layout data,and a curve of the normalized defect size distribution function, whichis made by inputting results of inspection of the manufacturing line.The obtained average fault ratio is used to predict the yield (SeePatent Document 1, for example).

Here, with respect to a relation between defect related yield Yr anddefects, various yield models have been proposed and evaluated (SeeNon-patent Document 1, for example). According to the Poisson yieldmodel, which assumes that defects occur uniformly at random positions ina wafer surface and their occurrence follows the Poisson distribution,the yield Yrb of a layer b is expressed by the following equation:

Yrb=exp(−Dob*θb*S)  (Eq. 1)

In this equation, Do_(b) is the total number of defects, which occur ina circuit layer b stacked in the pre-process) per unit area (totaldefect density), θ_(b) is an average fault ratio of the circuit layer b,and S is a chip area. It is difficult to know accurately the totaldefect density Do_(b) of the defects occurring in the circuit layer b.Thus, in practice, the performance-based total defect density Dob′ iscalculated using the actual yield Yrb′ of the circuit layer b, theaverage fault ratio θb and the chip area S. The calculated Do_(b)′ isused to obtain a electric fault density (Do_(b)′×θb) of the circuitlayer b, and then the electric fault density is multiplied by the chiparea S to calculate the defect related yield Yrb of the circuit layer b.Also, for each circuit layer (n) other than the circuit layer b, yieldYrn is calculated similarly. The yield of chips of the pre-process canbe obtained by multiplying the yields of all the circuit layers (SeePatent Document 1, for example).

On the other hand, the method by which the average fault ratio θ ofchips is calculated by obtaining the sum of the respective average faultratios of the circuit layers, and D0 is calculated from the actual yieldY and the chip area S according to the following equation Eq. 2 isdisclosed (Patent Document 2, for example).

ln(Y)=−D0*θ*S+ln(Ys)  (Eq. 2)

Here, Ys is yield resulting from characteristic failures. In a yieldmaturity period in which slight variation in circuit dimension, oxidefilm thickness and the like, as causes of characteristic failures, issuppressed, the second term ln(Ys) of Eq. 2 becomes 0. As a result, whenln(Y) calculated from the yield of the yield maturity period and θ*S areplotted for various kinds of products, then a curve with gradient (−D0)is obtained. Here, D0 is an average value of the total number of defectsthat occur in a line. Using D0, an average electric fault density of aproduct whose yield is to be predicted is calculated, and a goal of thedefect related yield can be calculated.

There is a method in which all the critical areas (each of which isobtained by multiplying an average fault ratio θ of the functional blockin question by an occupied area S of that functional block) offunctional blocks (such as an SRAM unit and a Logic unit) that can bearranged on a chip are obtained in advance, and an average fault ratioof the chip is calculated by dividing the sum of the respective criticalareas of the functional blocks by the sum of the occupied areas (SeePatent Document 3, for example).

Patent Document 1: Japanese Un-examined Patent Application Laid-Open No.2002-76086

Patent Document 2: Japanese Un-examined Patent Application Laid-Open No.2006-222118

Patent Document 3: Japanese Un-examined Patent Application Laid-Open No.2004-31891

Non-patent Document 1: James A. Cunningham, “The Use and Evaluation ofYield Models in Integrated Circuit Manufacturing”, IEEE Transactions onSemiconductor Manufacturing, Volume 3, Number 2, 1990

A gate array product is a semi-custom IC from which kinds of electronicdevices can be produced by connecting circuit elements (macro-cells)depending on requests of customers. In a gate array product, logic gatesare formed in a transistor formation layer and necessary gates only areconnected through a wiring layer. By preparing in advance a wafer calleda master that has been processed up to making a transistor formationlayer, there is a merit in that a product satisfying a request of acustomer can be manufactured and delivered in a short time. However,design layout data of the transistor formation layer have logic gatesthat are not ultimately connected. Accordingly, a result of calculationof an average fault ratio, using such design layout data as in theabove-mentioned Critical Area Analysis, leads to a larger value than theaverage fault ratio of an actual product.

Further, a gate array product is characterized by factors such as a chipsize, which determines an extent of the number of mountable logic gates,a logic part area ratio, i.e., a ratio of connected logic gates to chiparea, SRAM occupancy, i.e., a ratio of mounted SRAM parts to chip area.There are many products in which these factors are different. Thus, itis difficult to calculate average fault ratios of all circuit layers inall kinds of gate array products.

When the method described in Patent Document 3 is applied to a gatearray product, an average fault ratio is estimated by combining averagecritical areas of functional blocks mounted on a chip. Thus, it is notnecessary to calculate an average fault ratio from design layout data.However, this method does not consider connection lines between thefunctional blocks, and it is difficult to forecast an average faultratio considering effects of all the connection lines.

Further, also in the case of a cell-based IC in which previouslyprepared macro-cells are arranged and wired, random logic parts formedin the other areas than the arranged macro-cells are variously differentdepending on requests of customers. Thus, it is difficult to calculaterespective average fault ratios of the random logic parts.

Further, the conventional method of predicting yield is a method using atotal defect density Do calculated on the basis of an actual yield. Theactual yield is measured with respect to products manufactured in thepast. Accordingly, there is a time lag between the time when a wafer forwhich yield was measured flowed a production process of a circuit layerb and the time when a type of product whose yield is to be predictedflows in the production process of the circuit layer b. The total defectdensity Do has a decisive influence on the accuracy of yield prediction.Thus, although it is considered that the yield prediction of theconventional method is sufficiently accurate for pricing a product atthe time of receiving an order for the product, the accuracy of theconventional prediction method is low for controlling input.

The present invention has been made considering the above conditions. Anobject of the present invention is to provide a technique that canaccurately predict yield with respect to a semi-custom IC from whichkinds of electronic devices are manufactured by connecting circuitelements (macro-cells) depending on requests of customers, forappropriate pricing at the time of receiving an order for a product andappropriate controlling of input in the course of manufacturing anelectronic device.

SUMMARY OF THE INVENTION

According to the present invention, at the time of receiving an orderfor a semi-custom IC product from which various electronic devices aremanufactured by connecting circuit elements (macro-cells) according torequests of customers, the yield is calculated from the sum of averagefault ratios of a prescribed circuit layer, which are obtained fromvarious feature quantities of the yield calculation target product, anda total defect density D0 of the manufacturing line.

In detail, the present invention provides an electronic device yieldprediction system for predicting manufacturing yield of an electronicdevice, wherein: the electronic device yield prediction systemcomprises:

a defect density calculation unit, which calculates the total number ofdefects occurring in a manufacturing line; an average fault ratiocalculation unit, which calculates an average fault ratio that indicatesproportion of defects causing the electronic device to be failure, amongdefects occurring at the time of manufacturing; and a yield calculationunit, which calculates the manufacturing yield by using defect densityof the manufacturing line, which has been calculated by the defectdensity calculation unit, the average fault ratio of the electronicdevice, which has been calculated by the average fault ratio calculationunit, and a chip area of the electronic device; and wherein the averagefault ratio calculation unit uses an average fault ratio predictionmodel that calculates the average fault ratio by using productcharacteristics i.e. factors characterizing the electronic devices.

Further, according to the present invention, in the course ofmanufacturing a semi-custom IC product from which varieties ofelectronic devices are manufactured by connecting circuit elements(macro-cells) depending on requests of customers, the yield iscalculated from the average fault ratio of a prescribed circuit layer,which has been obtained from product characteristics of the yieldcalculation target product, and a electric fault density of a productdifferent from the yield prediction target product in wiring patterns,and an average fault ratio of a prescribed circuit layer, which has beenobtained similarly from the product characteristics.

In detail, the present invention provides an electronic device yieldprediction system for predicting a manufacturing yield of a firstelectronic device, wherein: the electronic device yield predictionsystem comprises: a electric fault density calculation unit, whichcalculates a electric fault density, i.e. a density of defects causingfailure among defects occurring in manufacturing, by usingactually-measured data, with respect to a second electronic devicedifferent from the first electronic device in wiring patterns and for apredetermined unit of time; an average fault ratio calculation unit,which calculates a first average fault ratio that indicates a ratio ofdefects causing the first electronic device to be failure and a secondaverage fault ratio that indicates a ratio of defects causing the seconddevice to be failure, among defects occurring in manufacturing; aelectric fault density translation unit, which calculates a electricfault density of the first electronic device by multiplying the electricfault density of the second electronic device, which has been calculatedby the electric fault density calculation unit, and a proportion of thefirst average fault ratio to the second average fault ratio together,with the first and second average fault ratio being calculated by theaverage fault ratio calculation unit; and a yield calculation unit,which selects, on a basis of a manufacturing history of a predictiontarget lot of a yield prediction target product, a electric faultdensity of a period in which the prediction target lot was processed,among electric fault densities calculated for the predetermined unit oftime and recorded by the electric fault density calculation unit, anduses the selected electric fault density to calculate the manufacturingyield; and the average fault ratio calculation unit uses an averagefault ratio prediction model that calculates an average fault ratio byusing product characteristics, i.e., factors characterizing the firstand second electronic devices.

According to the present invention, it is possible to predict the yieldat the time of receiving an order for a semi-custom IC product, inmanufacturing a wide variety of products in small quantities wherevarieties of electronic devices can be produced by connecting circuitelements (macro-cells) depending on requests of customers. As a result,it is possible to set prices appropriately. Further, since the yield canbe predicted accurately in the course of manufacturing, it is possibleto control input amounts appropriately.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of a yield predictionsystem according to one embodiment of the present invention;

FIG. 2 is a diagram for explaining an outline of a yield predictionprocedure;

FIG. 3 is a flowchart showing product characteristic storing processing;

FIG. 4 is a view showing an example of a variety;

FIG. 5 is a diagram showing an example of configuration of a productcharacteristic management table;

FIG. 6 is a flowchart showing average fault ratio storing processing;

FIG. 7 is a diagram showing an example of configuration of a functionalblock average fault ratio management table;

FIG. 8 is a diagram explaining a procedure for obtaining an averagefault ratio by the Critical Area Analysis;

FIG. 9 is a flowchart showing critical area calculation processing;

FIG. 10 is a flowchart showing average fault ratio prediction modeldatabase generation processing;

FIG. 11 is a diagram showing an example of configuration of an averagefault ratio prediction model database;

FIG. 12 is a flowchart showing actual yield storing processing;

FIG. 13 is a flowchart showing defect density D0 calculation processing;

FIG. 14 is a scatter diagram showing the logarithm of actual yield andcorresponding critical area of product;

FIG. 15 is a flowchart showing electric fault count calculationprocessing;

FIG. 16 is a flowchart showing yield prediction processing;

FIG. 17 is a flowchart showing functional block average fault ratiomanagement table generation processing;

FIG. 18 is a block diagram showing a configuration of a yield predictionsystem according to one embodiment of the present invention (Example 2);

FIG. 19 is a diagram explaining an outline of a yield predictionprocedure;

FIG. 20 is a diagram explaining an outline of calculation of yieldimpact;

FIG. 21 is a flowchart showing yield impact calculation processing;

FIG. 22 is a diagram showing an example of a yield impact managementtable;

FIG. 23 is a flowchart showing monthly average defect count calculationprocessing;

FIG. 24 is a flowchart showing monthly electric fault densitycalculation processing;

FIG. 25 is a diagram showing an example of a monthly electric faultdensity management table;

FIG. 26 is a flowchart showing product characteristic acquisitionprocessing;

FIG. 27 is a view showing an example of layout pattern of a gate arrayproduct;

FIG. 28 is a diagram showing an example of a product characteristicmanagement table;

FIG. 29 is a flowchart showing average fault ratio calculationprocessing;

FIG. 30 is a diagram showing an example of average fault ratioprediction model generation processing;

FIG. 31 is a diagram showing an example of an average fault ratioprediction model database;

FIG. 32 is a diagram showing an example of distribution of productcharacteristics of family products;

FIG. 33 is a diagram explaining a procedure for obtaining an averagefault ratio by the Critical Area Analysis;

FIG. 34 is a flowchart showing monthly electric fault densitycalculation processing of prediction target product;

FIG. 35 is a flowchart showing manufacturing history acquisitionprocessing;

FIG. 36 is a flowchart showing yield calculation processing;

FIG. 37 is a diagram explaining a procedure for obtaining a electricfault density;

FIG. 38 is a diagram explaining a procedure for obtaining a electricfault density;

FIG. 39 is a diagram explaining a procedure for obtaining a electricfault density;

FIG. 40 is a diagram showing an example of prediction of transition ofelectric fault density in a transistor formation layer; and

FIG. 41 is a diagram showing an example of comparison between apredicted value of the final yield and a measured value.

DETAILED DESCRIPTION Example 1

A yield prediction system of one embodiment of the present inventionwill now be described referring to the drawings.

The yield prediction system of the present embodiment predicts a yieldthat results from functional failures with respect to an electronicdevice product B (a prediction target product) at the time when an orderfor the product is received.

A configuration of the yield prediction system of the present embodimentwill be described. FIG. 1 is a block diagram showing a configuration ofthe yield prediction system of the present embodiment. As shown in thefigure, the yield prediction system 20 of the present embodiment isconnected to external units, namely, a optical inspection apparatus 21,an probe testing apparatus 23, an actual yield database 204′ and alayout database 24′ through a local area network 22.

The optical inspection apparatus 21 is an inline inspection apparatusthat detects defects such as dust particles and pattern defectsoptically in the course of wafer manufacturing. The probe testingapparatus 23 is a so-called tester that tests electrically defects of anelectric circuit of a chip on a wafer. The actual yield database 204′ isa database that retains yield of a wafer (i.e. a ratio of the number offunctional chips to the number of chips mounted on a wafer) tested bythe probe testing apparatus 23. The layout database 24′ is an apparatusthat retains a layout of a product, and, in the present embodiment,stores layout data (layout patterns) of the product, B and a group ofproducts produced in the past.

The yield prediction system 20 of the present embodiment comprises: adata input part 27 for receiving calculation conditions and the likefrom an operator; a data output part 26 for outputting data such as acalculation results to the outside; storage 200 for storing variousprograms and data for realizing yield prediction processing; a memory 28as a temporary storage; a processor 25 for loading the programs storedin the storage 200 into the memory 28 to execute the programs; and anetwork 29 connecting these component units.

The storage 200 stores: a product characteristic management table 201that manages product characteristics as factors characterizing aproduct; an average fault ratio prediction model database 202 forstoring average fault ratio prediction models (mentioned below); afunctional block average fault ratio management table 203′ for storingan average fault ratio (mentioned below) of a functional block; and ayield prediction program 205 for realizing yield prediction processing.

When the processor 25 loads the yield prediction program 205 into thememory 28 and executes the program 205, then the program 205 realizes: aproduct characteristic acquisition part that acquires productcharacteristics of a group of products from the product characteristicmanagement table 201; a functional block average fault ratio acquisitionpart that acquires average fault ratios of functional blocks mounted ona product from the functional block average fault ratio management table203′; a critical area calculation processing part that calculatescritical areas of the group of products by using the productcharacteristics of the group of products and the average fault ratioprediction model registered in the average fault ratio prediction modeldatabase 202; an actual yield acquisition part that acquires actualyields of the group of products from the actual yield database 204′; adefect density calculation processing part that calculates a defectdensity D0 of a manufacturing line from the actual yields and thecritical areas; a electric fault count calculation part that calculatesthe number of electric faults of a yield prediction target product fromthe defect density and the critical area of the yield prediction targetproduct; and a yield calculation part that calculates yield from thenumber of electric faults.

Next will be described an outline of a procedure in which the yieldprediction system 20 of the present embodiment obtains a defect densityof a manufacturing line on the basis of a relation between an actualyield and a critical area with respect to a group of products that havebeen already manufactured and then predicts a yield of the product B,i.e., the yield prediction target product, by using the critical area ofthe product B.

An outline of a yield prediction procedure of the present embodiment,which is performed through various functions respectively, will bedescribed. FIG. 2 is a diagram for explaining an outline of the yieldprediction procedure performed by the processing parts of the yieldprediction system 20 of the present embodiment.

First, the product characteristic acquisition part acquires productcharacteristics of products manufactured in the past from the productcharacteristic management table 201 (Step 11′). Product characteristicsare quantities indicating a configuration of a variety of chip, andcomprises: a chip size; an inner area size that is an area sizeexcluding an I/O part positioned in the periphery of the chip; names andthe number of macro-cells mounted in the inner area; a basic cellemployment ratio, i.e., a ratio of basic cells used for logic circuitsamong basic cells that are laid over the inner area except for the areasof the macro-cells; an I/O cell height; and a mask area ratio, i.e., aratio of a mask area in an upper wiring layer to the chip area.

Further, the functional block average fault ratio acquisition partacquires in transistor formation layers and lower wiring layers averagefault ratios and sizes of functional blocks mounted in the group ofproducts for which the product characteristics have been acquired, fromthe functional block average fault ratio management table 203 (Step12′).

Then, the critical area calculation processing part for calculating thecritical areas of the group of products calculates critical areas foreach layout layer by using the average fault ratio prediction models forthe group of products, which are registered in the average fault ratioprediction model database 202 (Step 13′). Average fault ratio predictionmodels for a transistor formation layer and a lower wiring layercalculate critical areas of a chip, as the total sum of critical areasof functional blocks mounted on the chip, while an average fault ratioprediction model for an upper wiring layer is a regression model thatpredicts an average fault ratio on the basis of a mask area ratio.

Next, the actual yield acquisition part acquires actual yields of thegroup of products for which the critical areas have been calculated,from the actual yield database (Step 14′). Then, a gradient −D0 isacquired from a scatter diagram with axes of a logarithm of actual yieldand a total sum of critical areas, to acquire an average defect densityof a manufacturing line.

Next, the critical area of the product B as the prediction targetproduct is calculated by the product characteristic acquisition part forthe product B (Step 16′), the average fault ratio acquisition part forthe functional blocks (Step 17′), and the critical area calculation partfor the product B (Step 18′). The number of electric faults of theproduct B is calculated from the average defect density of themanufacturing line and the critical areas of the product B (Step 19′).Then, based on the number of electric faults, yield of the product B iscalculated by using Poisson's yield prediction formula, for example(Step 101).

By the above steps, yield Y_(B) of the product B can be predicted at thetime of receiving an order for the product on the basis of the averagedefect occurrence density D0 of the manufacturing line and the productcharacteristics and the average fault ratios of the functional blocks ofthe product B.

Next, operation of the yield prediction system of the present embodimentwill be described in detail for each of Steps 11′-101 shown in FIG. 2.

Product characteristic acquisition processing (Steps 11′ and 16′ of FIG.2) performed by the product characteristic acquisition part will bedescribed. FIG. 3 shows a flow of the product characteristic acquisitionprocessing of the present embodiment. In the product characteristicacquisition processing, product characteristics of the group of productsand product characteristics of the product B are acquired from theproduct characteristic management table 201 and stored into the memory(Step 301).

FIG. 4 is a conceptual diagram showing a configuration of a variety.Quantities that characterize a variety are chip size, an inner area sizeobtained by subtracting an I/O part from the chip size, kinds andnumbers of macro-cells mounted in the inner area, a basic cellemployment ratio (i.e., a ratio of the number of used basic cells forlogic circuits to the number of laid basic cells over the area obtainedby subtracting the macro-cell occupancy from the inner area), an I/Ocell height, and a mask area ratio (i.e. a ratio of the wiring area tothe chip area). FIG. 5 explains an example of the product characteristicmanagement table 201. As product characteristics that characterize eachproduct, the product characteristic management table 201 stores chipsize (mm), an inner area size (mm), kinds and number of mountedmacro-cells, a basic cell employment ratio (%), and an I/O cell heightfor each product. Further, since global wiring for connectingmacro-cells increases in an upper wiring layer of a chip, it is notpossible to estimate a critical area of a chip by considering onlycontributions of individual functional blocks. Thus, a mask area ratiois taken as a product characteristic for an upper wiring layer, insteadof an average fault ratio and occupancy of functional blocks.

Functional block average fault ratio storing processing (Steps 12′ and17′ in FIG. 2) will be described. FIG. 6 is a flow of the average faultratio storing processing of the present embodiment. In the average faultratio storing processing, an average fault ratio and each size for eachlayout layer of functional blocks as a component of a product is storedinto the memory (Step 601).

FIG. 7 shows an example of the functional block average fault ratiomanagement table 203′. Functional blocks described in the functionalblock average fault ratio management table 203′ are macro-cells and theI/O part mounted in the group of products and the product B. The size ofa functional block is a value obtained from design data stored in thelayout database. An average fault ratio of a functional block isobtained by performing the CAA simulation that uses the conventionalCritical Area Analysis. The CAA simulation, i.e., the Critical AreaAnalysis is a well-known method, and its procedure is described onlysimply here. FIG. 8 is a diagram explaining a procedure for obtaining anaverage fault ratio by the Critical Area Analysis.

The Critical Area Analysis is a method that comprises a step in whichcircuit pattern layout data are inputted to generate a curve 41 offailure probability against defect diameter (FIG. 8( a)), a step inwhich inspection result data in a manufacturing line is inputted togenerate a defect occurrence rate curve (the normalized defect sizedistribution curve) 42 or the normalized defect size distribution curve42 is generated by using a formula (FIG. 8( b)). The Critical AreaAnalysis obtains a hatched part 43 from a product-sum of these twocurves 41 and 42 (FIG. 8( c)) to obtain an average fault ratio θ.

The curve 41 in FIG. 8( a) shows that larger the diameter of a defectis, the higher the probability of failure (short circuit or breaking) ina circuit pattern. Further, it is known that defects occurring in amanufacturing line are expressed by F(x)=(n−1)·x_(o) ^(n−1)·x^(−n),where F(x) is an occurrence rate, x is a diameter of a defect, and n isa defect size distribution parameter. The curve 42 in FIG. 8( b) isdepicted according to this formula. The product of the curve 41 and thecurve 42 is obtained, and then the integral of the product from theminimum diameter x₀ to infinity leads to the area of the hatched part 43of FIG. 8( c). By this, it is possible to obtain an average fault ratioθL of an L layout layer of a macro-cell A of the product B, for example.

Here, functional block average fault ratio management table generationprocessing will be described referring to FIG. 17. First, in thefunctional block average fault ratio management table generationprocessing, average fault ratios of the macro-cells and the I/O part ineach layout layer of the transistor formation layer and the lower wiringlayer are calculated by the CAA simulation with respect to a varietydesignated in advance (Step 1701).

Next, for each macro-cell, the size of the macro-cell and respectiveaverage fault ratios for the layout layers are collected together (Step1702). Since the area occupied by the I/O part is different depending ona chip size, with the size item of the I/O part not inputted, only therespective average fault ratios for the layout layers are stored in thefunctional block average fault ratio management table 203′ (Step 1703).

Next, the critical area calculation processing (Steps 13′ and 18′ inFIG. 2) performed by the critical area calculation processing part willbe described. FIG. 9 shows a flow of the critical area calculationprocessing of the present embodiment.

The critical area calculation processing part acquires average faultratio prediction models for all the layers from the average fault ratioprediction model database 202 and stores the acquired models into thememory 28 (Step 901).

Here, processing flow of generating the average fault ratio predictionmodel database to which the critical area calculation processing partrefers will be described referring to FIG. 10.

First, the CAA simulation is performed with respect topreviously-designated several varieties having different basic cellemployment ratios, to calculate average fault ratios θ_(Logic) of randomlogic parts of circuit patterns of the transistor formation layers andthe lower wiring layers (Step 1001).

Next, with respect to the circuit patterns of the transistor formationlayers and the lower wiring layers, an average fault ratio predictionformula of a random logic part is derived by regression analysis using abasic cell employment ratio as an explanatory factor, and thus modelcoefficients C1 and C2 are determined (Step 1002).

θ_(Logic)=Function(basic cell employment ratio)=C1×basic cell employmentratio+C2  (Eq. 3′)

Next, with respect to the transistor formation layers and the lowerwiring layers, the total sum of critical areas of the macro-cells, theI/O part and the random logic part as components of a chip is obtained.Then, an average fault ratio prediction model that obtains an averagefault ratio by dividing the above-obtained total sum by the chip area isgenerated and stored into the average fault ratio prediction modeldatabase 202 (Step 1003).

Average fault ratio=(Σ(θi×Ai)+θIO×AIO+Function(basic cell employmentratio)×Alogic)/A  (Eq. 4′)

where θi is an average fault ratio of a macro-cell, Ai is an areaoccupied by a macro-cell, θIO is an average fault ratio of the I/O part,AIO is an area occupied by the I/O part, Function(basic cell employmentratio) is an average fault ratio θ Logic of a random logic part, whichis determined by a basic cell employment ratio, and A is a chip area.

As for upper wiring layers, the CAA simulation is performed with respectto previously-designated several varieties having different mask arearatios, to calculate an average fault ratio of chips (Step 1004).

As for upper wiring layers, an average fault ratio prediction formulahaving a mask area ratio as an explanatory factor is derived byregression analysis, to determine model coefficients C3 and C4 (Step1005). The derived formula is stored into the average fault ratioprediction model database 202 (Step 1006).

Average fault ratio of an upper wiring layer=C3×mask area ratio+C4  (Eq.5′)

The average fault ratio prediction model database 202 is completed asdescribed above, and is stored into the storage 200. FIG. 11 shows anexample of the average fault ratio prediction model database 202. Oneaverage fault ratio prediction model is generated for each layout layerof the group of products of many varieties different in productcharacteristics (a chip size, an inner area size, a basic cellemployment ratio, kinds of mounted macro-cells, the number of mountedmacro-cells, and a mask area ratio). As for the transistor formationlayers (layer L and layer FG) and the lower wiring layers (M1-M3), thecritical area of a chip is calculated as the total sum of critical areasof the macro-cells, the I/O part and the random logic part as componentsof the chip, and each model calculates an average fault ratio based onthe critical area of the chip. As for the upper wiring layers (M4-M8),it is difficult to predict the average fault ratio of a chip on thebasis of only contributions of the components of the chip. Thus, in thiscase, a prediction model is a prediction regression model that obtainsthe average fault ratio of a chip from the mask area ratio which is anindex of wiring complexity.

The critical area calculation processing part substitutes productcharacteristics into an average fault ratio prediction model, tocalculate an average fault ratio for each layout layer of a product.Then, a critical area is calculated by multiplying the obtained averagefault ratio by the chip area. For each product, a total sum of criticalareas for each layout layer is obtained and stored into the storage 200(Step 902 of FIG. 9).

Next, actual yield storing processing (Step 14′ of FIG. 2) will bedescribed. FIG. 12 shows flow of the actual yield storing processing ofthe present embodiment. In the actual yield storing processing, actualyields of the group of products for which the total sums of criticalareas have been calculated are obtained from the actual yield database204′ and stored into the storage 200 (Step 1201).

A defect density D0 calculation part (Step 15′ of FIG. 2) will bedescribed. FIG. 13 shows flow of defect density D0 calculationprocessing. In the defect density calculation processing, a logarithm ofactual yields of the group of products is calculated and stored into thestorage (Step 1301). Next, a logarithm of actual yield-critical areascatter diagram is generated as shown in FIG. 14. A relation betweenlogarithm of actual yield and critical area is approximated by a line.Thus, a level D0 of defects occurring in the manufacturing line isestimated and stored into the storage (Step 1302).

Next, the electric fault count calculation part that calculates thenumber of electric faults with respect to the product B (Step 19′ ofFIG. 2) will be described. FIG. 15 shows flow of electric fault countcalculation processing. In the electric fault count calculationprocessing, the number of electric faults with respect to the product Bis calculated by the following formula on the basis of the defectdensity D0 of the manufacturing line and the critical area of theproduct B (Step 1501).

The number of electric faults of the product B=defect density D0 of theline×critical area of the product B  (Eq. 6′)

Next, a predicted yield calculation processing part (Step 101 of FIG. 2)for the product B will be described. FIG. 16 shows flow of predictedyield calculation processing. The predicted yield calculation processingpart calculates a predicted yield of the product B by using the numberof the electric faults of the product B, and stores the result into thestorage (Step 1601).

Predicted yield YB=exp(−1×the number of electric faults)×100  (Eq. 7′)

The result of yield prediction in the storage is read and outputtedthrough the data output part (Step 1602).

As described above, the yield prediction system of the presentembodiment can easily predict an average fault ratio of the yieldprediction target product B from the product characteristics, andcalculate a predicted yield Y_(B) of the product B, which reflects theaverage defect density D0 of the manufacturing line, at the time ofreceiving an order for the product. In other words, it is possible topredict yield with high accuracy and to set an appropriate price in viewof sufficient profit, at the time of receiving an order for anelectronic device product in manufacturing of a wide variety of productsin small quantities by connecting circuit elements (macro-cells)depending on requests of customers.

The above embodiment judges a fault-probability owing to defects only onthe basis of diameter of a defect. The present invention is not limitedto this. For example, an average fault ratio prediction model may bederived based on a failure ratio calculation result that considers up toremedy allowing for potential of a circuit pattern.

Example 2

Next, another yield prediction system of one embodiment of the presentinvention will be described referring to drawings.

The yield prediction system of the present embodiment predicts a yieldthat results from functional failures, in the course of manufacturing anelectronic device product B (a prediction target product).

In the present embodiment, optical inspection and electrical inspectionare performed on another product A (a reference product) that hasalready been produced on the manufacturing line, and these inspectionresults are used for prediction of a yield of the product B. Here, it isassumed that the product A and the product B are family productsmanufactured in similar processes. In detail, it is assumed that theproduct A and the product B have the same stacked layer structurealthough their circuit patters are different, each having structure ofstaking of one or more circuit layers a, b, c, . . . in order. Further,it is also assumed that the product A and the product B are similar inmaterials constituting each circuit layer, and also similar in filmformation method, exposure method, etching method, and the like,employed for forming each circuit layer. However, respective wiringpatterns (including spaces between lines) of circuit layers of theproduct A and the product B are completely different from each other.

The present embodiment will be described taking, as an example, the casewhere each of the products A and B is an LSI formed on a wafer, and ayield of a circuit layer c (hereinafter, referred to as the layer c) ofthe product B is predicted among one or more circuit layers stacked asdescribed above. Prediction of another circuit layer is similar. Yieldof the product B as a whole can be obtained by calculating the productof the respective yields of the layers.

A configuration of the yield prediction system of the present embodimentwill be described. FIG. 18 is a block diagram showing the yieldprediction system of the present embodiment. As shown in the figure, theyield prediction system of the present embodiment is connected toexternal units, namely, a optical inspection apparatus 21, a probetesting apparatus 23 and a CAD system 24 through a local area network22.

The optical inspection apparatus 21 is an inline inspection apparatusthat detects defects such as dust particles and pattern defectsoptically in the course of wafer manufacturing. The probe testingapparatus 23 is a so-called tester that electrically tests for defectsof an electric circuit of a chip on a wafer. The CAD system 24 is anapparatus for designing and developing a layout of a product. In thepresent embodiment, the CAD system 24 stores layout data (i.e., layoutpatterns) of the products A and B.

The yield prediction system 20 of the present embodiment comprises: adata input part 26 for receiving calculation conditions and the likefrom an operator; a data output part 27 for outputting data such as acalculation results to the outside; a storage 200 for storing variousprograms and data for realizing yield prediction processing; a memory 28as a temporary storage; a processor 25 for loading the programs storedin the storage 200 into the memory 28 to execute the programs; and anetwork 29 connecting these component units.

The storage stores: a product characteristic management table 201 thatmanages product characteristics as factors characterizing a product; anaverage fault ratio prediction model database 202 for storing averagefault ratio prediction models (mentioned below); a yield impactmanagement table 203 for storing yield impact (mentioned below) of theproduct A; a monthly defect density management table 204 for storing amonthly defect density (mentioned below) of the product A; and a yieldprediction program 205 for realizing yield prediction processing.

When the processor 25 loads the yield prediction program 205 into thememory 28 and executes the program 205, then the program 205 realizes: ayield impact calculation processing part that calculates yield impact,i.e., a degree of impact of one defect in a prescribed layer of analready-manufactured product, on yield; a monthly average defect countcalculation processing part that calculates the monthly average numberof defects in a predetermined layer of an already-manufactured product;a monthly electric fault density calculation processing part thatcalculates monthly electric fault density, i.e., the density of electricfaults (defects as causes of a failure product) in a predetermined layerof an already-manufactured product; a product characteristic acquisitionpart that acquires product characteristics of a product; an averagefault ratio calculation processing part that calculates an average faultratio θ, i.e., a ratio of electric faults (defects as causes of afailure product) among defects occurring in a predetermined layer of aproduct at the time of manufacturing; a prediction target productmonthly electric fault density calculation processing part thatcalculates monthly electric fault density of a prediction target layerof a yield prediction target product; a manufacturing historyacquisition processing part that acquires a manufacturing history of aprediction target lot of the yield prediction target product; and ayield calculation processing part that calculates yield of theprediction target layor of the prediction target lot of the yieldprediction target product.

Next will be described an outline of a procedure in which the yieldprediction system 20 of the present embodiment performs opticalinspection and electrical inspection on another product A that has beenalready manufactured in the manufacturing line, and the inspectionresults are used for predicting yield of the product B.

Now, an outline of a yield prediction procedure of the presentembodiment, which is performed through various functions respectively,will be described. FIG. 19 is a diagram for explaining yield predictionprocedure performed by the processing parts of the yield predictionsystem 20 of the present embodiment.

First, the yield impact calculation processing part calculates yieldimpact of the layer c of the product A (Step 11). Here, opticalinspection result data 31 of the layer c of the product A, which arestored in the optical inspection apparatus 21, and electrical inspectionresult data 35 of the product A, which are stored in the probe testingapparatus 23, are used to calculate the probability (i.e. yield impact)KRc that an LSI chip of the product A becomes a fail chip owing to onedefect in the layer c. The yield impact calculation processing partperforms this processing with respect to a plurality of wafers, tocalculate an average yield impact KRc owing to a defect in the layer cof the product A. The yield impact KR is a quantity that indicates thesensitivity of layout to defect, and accordingly it is sufficient tocalculate an average yield impact KR once for a plurality of wafers.

Further, the monthly average defect count calculation processing partcalculates the monthly average number of defects of the layer c of theproduct A (Step 12). Here, the monthly average defect count calculationprocessing part reads the optical inspection result data 31 obtained forone month in the step where the product A is manufactured up to thelayer c from the external optical inspection apparatus 21 through thenetwork 22. Then, after screening abnormal value out of the opticalinspection result data 31, the obtained value is calculated as themonthly average number of defects. The processing of calculating monthlyaverage number of defects is performed every month.

The monthly electric fault density calculation processing partcalculates a monthly electric fault density, i.e., the number ofelectric faults (defects causing a failure product) per unit area amongdefects in the layer c of the product A, by using the yield impact KRcof the layer c of the product A (which has been calculated by the yieldimpact calculation processing part) and a monthly average defect densityobtained by dividing the monthly average number of defects (which hasbeen calculated by the monthly average defect count calculationprocessing part) by the inspected area (Step 13). The density of defectscausing a failure product in the layer c of the product A can becalculated by multiplying the probability that one defect in the layer cof the product A causes a failure product by the average defect densityof the defects occurred in the layer c in the month in question.

Next, with respect to each of the products A and B, the productcharacteristic acquisition processing part acquires productcharacteristics as factors characterizing a gate array product from theproduct characteristic management table 201 (Steps 14 and 15). Theproduct characteristics include, for example, a chip size thatdetermines the extent of the number of mountable logic gates, a logicpart area ratio, i.e., a ratio of connected logic gates to chip area, anSRAM occupancy, i.e., a ratio of a mounted SRAM parts to chip area, andthe like.

Then, the average fault ratio calculation processing part calculates anaverage fault ratio θ_(A) of the layer c of the product A by using theproduct characteristics of the product A, which have been obtained bythe product characteristic acquisition processing part, and thebelow-mentioned average fault ratio prediction model (Step 16). Further,the average fault ratio calculation processing part calculates anaverage fault ratio θ_(B) of the layer c of the product B by using thesame average fault ratio prediction model and the productcharacteristics of the product B (Step 17). The method of calculationwill be described later.

Next, the prediction target product monthly electric fault densitycalculation processing part calculates a monthly electric fault densityof the layer c of the product B from a ratio of the average fault ratioθ_(A) of the layer c of the product A to the average fault ratio θ_(B)of the layer c of the product B, which have been calculated by theaverage fault ratio calculation processing unit, and the monthlyelectric fault density of the layer c of the product A, which has beencalculated by the monthly electric fault density calculation processingpart (Step 18). The product A and the product B are productsmanufactured by the same process. Thus, the electric fault density ofthe month in question, which corresponds to the product of the totalnumber of defects occurring in the layer c and the average fault ratioθ_(B) of the layer c, can be calculated by multiplying the monthlyelectric fault density of the layer c of the product A by a ratioθ_(B)/θ_(A) of the average fault ratio θ_(B) of the layer c of theproduct B to the average fault ratio θ_(A) of the layer c of the productA.

Further, the manufacturing history acquisition processing part acquiresthe month in which processing of the layer c has been performed withrespect to a lot B1 as the target lot of prediction of yield of theproduct B from the manufacturing history of the lot B1 (Step 19). Here,the manufacturing history means the month of the launch of transistorformation layer, the month of the launch of wiring layer, and theexpected month of electrical inspection, i.e., the month of yieldprediction. Input of manufacturing history is received from the operatorthrough the data input part 26.

The yield calculation processing part calculates yield Y_(BC) of thelayer c of the lot B1 of the product B from the monthly electric faultdensity of the layer c of the product B of the month in question, whichhas been derived from the monthly electric fault density calculationprocessing part and the manufacturing history of the lot B1 by using thePoisson's yield prediction formula (Step 20).

Thus, according to the above-described steps, it is possible to predictthe yield Y_(B) of the layer c of the lot B1 of the product B in thecourse of manufacturing, by the calculation based on the opticalinspection result on the layer c of the product A, the electricalinspection result on the same wafer for which the optical inspectionresult has been obtained, the monthly average number of defects in thelayer c of the product A, the product characteristics of the product A,the product characteristics of the product B, and the manufacturinghistory of the lot B1.

Next, operation of the yield prediction system of the present embodimentwill be described in detail for each of Steps 11-20 shown in FIG. 19.

First, yield impact calculation processing performed by the yield impactcalculation processing part will be described (Step 11 of FIG. 19).

First, an outline of the processing of calculation of the yield impactKRc from the optical inspection result data 31 and the electricalinspection result data 35 of the layer c of the product A will bedescribed. Here, the impact on the yield of the layer c as the yieldprediction target layer is obtained by calculating a ratio of good chipsaffected by a defect and a ratio of good chips affected by the otherprocesses on the basis of the mentioned data. FIG. 20 is a diagramexplaining an outline of the calculation of the yield impact KRaccording to the present embodiment.

First, the yield impact calculation processing part reads the opticalinspection result data 31 of the product A from the optical inspectionapparatus 21 and the electrical inspection result data 35 of the productA from the probe testing apparatus 23.

The optical inspection result data 31 are data as a result of opticalinspection performed in the step where the product A has beenmanufactured up to the layer c. As shown in FIG. 20, the opticalinspection result data 31 shows the LSI chips 33 in which defects 34exist, among the LSI chips formed on a wafer 32. The optical inspectionresult data 31 include a product name, an inspection process name, a lotnumber, a wafer number, defect coordinate data, and the like.

Further, the electrical inspection result data 35 are data as a resultof inspection performed by the probe testing apparatus 23 to see whethera chip is good (pass) or bad (fail), in the step where all the circuitpatterns are formed on a wafer 32 of the product A. As shown in FIG. 20,the electrical inspection result data 35 show locations of chips thatare electrically defective among the LSI chips 33 formed on the wafer32. The electrical inspection result data 35 include product name, testname, lot number, wafer number, chip quality (pass or fail), and thelike.

The yield impact calculation processing part calculates a ratio Yp ofgood chips affected by the defects detected in the layer c, by using theoptical inspection result data 31. Here, chips on which defects 34 exist(chips with defect) are extracted from the chips 33 on the wafer 32, andthe number of the chips with defect is counted. Next, the data 37 thatspecify the chips on which the defects 34 exist are compared with theelectrical inspection result data 35. Among the chips with a defect inthe layer c, the number of chips that are finally judged to be good bythe electrical inspection result is counted. In the example of FIG. 20,five chips have a defect in the layer c. Among them, two chips arejudged to be good by the electrical inspection result. Then, a ratio ofthe number of good chips to the number of chips with a defect iscalculated and obtained as the ratio Yp of good chips affected bydefects in the layer c.

Further, the yield impact calculation processing part calculates a ratioYnp of good chips affected by other processes with respect to a specificlayer (here, assumed as the layer c), by using the optical inspectionresult data 31. Here, among the chips 33 on the wafer 32, chips on whichno defect 34 exists (chips without defect) are extracted, and the numberof the chips without defect is counted. The result of the extraction isshown in the hatched part of the data 38 in FIG. 20. Next, the data 38are compared with the electrical inspection result data 35, and thenumber of chips that are finally judged to be good chips by theelectrical inspection result is counted among the chips without a defectin the layer c. In the example of FIG. 20, twenty chips have no defectin the layer c, and, among these chips, eighteen chips become good chipsas a result of the electrical inspection. A ratio of the good chips tothe chips without defect is calculated to obtain the ratio Ynp of goodchips affected by defects other than those in the layer c.

Then, a ratio of good chips affected only by the defects in the layer ccan be determined by dividing the ratio Yp of good chips affected by thedefects of the layer c by the ratio Ynp of good chips affected by theother defects than ones in the layer c. As a result, 1−Yp/Ynp indicatesa ratio of failure chips owing to only the defects in the layer c, thatis to say, the impact of one defect on the layer c on the yield.

The above processing will be described as processing flow. FIG. 21 showsflow of the yield impact calculation processing of the presentembodiment. The present processing can be performed at any time beforethe monthly electric fault density calculation processing calculates themonthly electric fault density. Here, it is assumed that the processingis started being triggered by user's input of designation of the layer cof the product A.

The yield impact calculation processing part receives designation of thetarget of the yield impact storing processing, i.e., the layer c of theproduct A through the data input part 26 (Step 71).

Next, the yield impact calculation processing part extracts the opticalinspection result data 31 (which include defect coordinate data of thelayer c of the product A) stored in the optical inspection apparatus 21,and receives the extracted data through the network 22 and the datainput part 26, and stores the data into the memory 28 (Step 72). By theprocessing of Step 72, the optical inspection result data 31 thatindicate on which LSI chips 33 the defects 34 exist in the layer c,among the LSI chips 33 of the product A formed on the wafer 32, can bestored into the memory 28.

Next, the yield impact calculation processing part extracts theelectrical inspection result data 35 with respect to the same wafer ofthe optical inspection result data 31 obtained in Step 72 from the probetesting apparatus 32, and receives the extracted data through thenetwork 22 and the data input part 26, and stores the data into thememory 28 (Step 73). By the processing of Step 73, the data 35 thatindicate on which LSI chips 33 the electrical defects exist among theLSI chips 33 of the product A formed on the wafer 32 can be stored intothe memory 28.

Next, the yield impact calculation processing part uses the opticalinspection result data 31 and the electrical inspection result data 35to calculate the ratio of the number of good chips among chips with adefect in the layer c, to obtain the ratio Yp of good chips affected bythe defects in the layer c, as described referring to FIG. 20 (Step 74).

Further, using the optical inspection result data 31 and the electricalinspection result data 35, the yield impact calculation processing partcalculates the ratio of the number of good chips among chips withoutdefect in the layer c, to obtain the ratio Ynp of good chips affected bythe other causes than the defects in the layer c, as described referringto FIG. 20 (Step 75).

Then, as described referring to FIG. 20, the ratio Yp of good chipaffected by defects in the layer c and the ratio Ynp of good chipsaffected by the other causes than the defects in the layer c are used tocalculate 1−Yp/Ynp, to obtain the ratio of fail chips owing only to thedefects in the layer c, i.e. the yield impact KRc of one defect in thelayer c (Step 76).

Yield impacts KRc of the layer c of the product A are calculated usinginspection results of a plurality of wafers, and their average value isstored into the yield impact management table 203 of the product A (Step77).

Here, a configuration of the yield impact management table 203 will bedescribed. The yield impact management table 203 manages yield impactsin association with names of layers of a product for which yield impactKR is calculated. FIG. 22 shows an example of the yield impactmanagement table 230 of the present embodiment. As shown in the figure,the yield impact management table 203 has: a layer name storing column2031 for registering a name (a layer name) specifying a layer for whichyield impact has been calculated; and a yield impact storing column 2032for registering yield impact KR calculated with respect to the layerstored in the layer name storing column according to the above-describedprocedure. In Step 77, yield impact KRc is stored in association withthe layer c.

Next, monthly average defect count calculation processing (Step 12 ofFIG. 19) performed by the monthly average defect count calculation part.FIG. 23 shows flow of the monthly average defect count calculationprocessing of the present embodiment. This processing is performedmonthly in order to reflect a situation of occurrence of defects in themanufacturing line on the predicted value of yield.

As shown in the figure, the monthly average defect count calculationprocessing part uses a calendar function or the like of the yieldprediction system 20 to start the processing when predetermined date andtime has come. Here, it is assumed, for example, that the processing isstarted at a predetermined time of the first day of each month.

The monthly average defect count calculation processing extracts defectcoordinate data registered the previous month among defect coordinatedata stored within the optical inspection apparatus 21 with respect tothe layer c of a group of products that are manufactured by a processsimilar to the process for the product A, and then stores the extracteddata as the optical inspection result data 31 into the memory 28 via thelocal network 22 and the data input part 26 (Step 92). In the case wherethe present processing is to be performed not on the first day of themonth, it is sufficient to extract defect coordinate data that have beenregistered for one month before the date on which the present processingis to be performed.

The monthly average defect count calculation processing part calculatesthe total number of defects and its standard deviation σ of the defectcoordinate data in the memory 28. Then, using only wafers for which thetotal number of defects is the average value ±2σ, the monthly averagedefect count calculation processing part takes the average to calculatethe monthly average number of defects. The calculated monthly averagenumber of defects is stored into the memory 28 (Step 93).

Next, monthly electric fault density calculation processing (Step 13 ofFIG. 19) performed by the monthly electric fault density calculationprocessing part will be described. FIG. 24 shows a flow of the monthlyelectric fault density calculation processing of the present embodiment.This processing is performed monthly in order to reflect a situation ofoccurrence of electric faults in the layer c on the predicted value ofyield.

As shown in the figure, the monthly electric fault density calculationprocessing part uses the calendar function or the like of the yieldprediction system 20 to start the processing when predetermined date andtime has come. Here, it is assumed, for example, that the processing isstarted at a predetermined time of the first day of each month. Forexample, the processing may be started being triggered by the monthlyaverage defect count calculation processing part calculating the monthlyaverage number of defects and storing it into the memory 28.

As the monthly electric fault density D_(AC) of the layer c of theproduct A, KRc×(monthly average number of defects)/(S_(A)×N) iscalculated by using the yield impact KRc of the layer c (which has beenstored in the yield impact management table 203 of the product A), themonthly average number of defects in the layer c (which is in the memory28), the chip area S_(A) of the product A, and the number N of chips ona wafer of the product A. The calculated monthly electric fault densityD_(AC) is stored in the monthly electric fault density management table204 of the product A (Step 102).

Here, a configuration of the monthly electric fault density managementtable 204 will be described. The monthly electric fault densitymanagement table 204 is generated for one product that is taken as thestandard for yield prediction. FIG. 25 shows an example of the monthlyelectric fault density management table 204 of the present embodiment.As shown in the figure, the monthly electric fault density managementtable 204 stores the electric fault density of each layer for eachmonth. The monthly electric fault density management table 204 has: alayer name storing column 2041 for registering a name (a layer name) ofa layer for which the electric fault density has been calculated; and aelectric fault density storing column 2042 for storing the electricfault density of each layer for each month.

In the calculation of Step 102, the monthly electric fault densitycalculation processing part obtains the chip area S_(A) of the product Afrom the below-described product characteristic management table 201 andthe number N of chips on a wafer 32 of the product A is given in advanceas a fixed value. Or, the number N may be stored in the below-describedproduct characteristic management table 201.

Next, product characteristic acquisition processing (Steps 14 and 15 ofFIG. 19) performed by the product characteristic acquisition processingpart will be described. FIG. 26 shows a flow of the productcharacteristic acquisition processing of the present embodiment.

Product characteristics of the product A as the reference product andproduct characteristics of the product B as the prediction targetproduct are acquired from the product characteristic management table201 and stored into the memory 28 (Step 121).

Here, a configuration of the product characteristic management table 201will be described. As product characteristics that characterize eachproduct, the product characteristic management table 201 stores a chipsize (cm), an SRAM occupancy (%) and a logic part area ratio (%) foreach product. From these pieces of information, a chip area, an SRAMpart area (i.e. an area occupied by an SRAM part), a logic part area(i.e., an area occupied by a logic part) and an area of a non-used partare clearly known. FIG. 27 shows an example of design layout of a gatearray product of the present embodiment. As shown in the figure, thearea S_(SRAM) occupied by the SRAM part is obtained by (SRAMoccupancy×chip area), and the area S_(Logic) occupied by the logic partis obtained by (logic part area ratio×chip area).

FIG. 28 shows an example of the product characteristic management table201. The product characteristic management table 201 has a variety namecolumn 2011 for storing a product name and a feature quantity storingcolumn 2012 for storing feature quantities of each product. Productcharacteristics managed by the product characteristic management table201 are not limited to those shown in the figure. For example, the table201 may store the above-mentioned number of chips or the below-mentionedwiring area.

Next, average fault ratio calculation processing (Steps 16 and 17 ofFIG. 19) performed by the average fault ratio calculation processingpart will be described. FIG. 29 shows a flow of the average fault ratiocalculation processing of the present embodiment.

The average fault ratio calculation processing part acquires the averagefault ratio prediction model for a circuit pattern of the layer c fromthe average fault ratio prediction model database 202, and stores theacquired model into the memory 28 (Step 141).

Here, average fault ratio prediction model database generationprocessing referred to by the average fault ratio calculation processingpart will be described referring to FIGS. 30 to 33.

FIG. 30 shows a flow of average fault ratio prediction model generationprocessing.

The average fault ratio calculation processing part performs the CAAsimulation with respect to a previously-designated variety to calculatean average fault ratio θ_(SRAM) for circuit patterns of transistorformation layers and lower wiring layers and an average fault ratioθ_(Logic) for logic parts (Step 241).

The average fault ratio calculation processing part stores an averagefault ratio prediction model

θ×S=θ _(SRAM) ×S _(SRAM)+θ_(Logic) ×S _(Logic)  (Eq. 2)

for circuit patterns of the transistor formation layers and the lowerwiring layers into the average fault ratio prediction model database 202(Step 242).

The average fault ratio calculation processing part performs the CAAsimulation with respect to previously-designated varieties havingdifferent product characteristics, to calculate an average fault ratio θof chips in circuit patterns in intermediate wiring layers (Step 243).

The average fault ratio calculation processing part derives an averagefault ratio prediction model having an SRAM area and a Logic area asexplanatory factors by the regression analysis, to determine modelcoefficients C1, C2 and C3 (Step 244).

The average fault ratio calculation processing part stores the averagefault ratio prediction model

θ×S=C1×S _(SRAM) +C2×S _(Logic) +C3  (Eq. 3)

for the circuit patterns in the intermediate wiring layers into theaverage fault ratio prediction model database 202 (Step 245).

The average fault ratio calculation processing part performs the CAAsimulation with respect to previously-designated varieties havingdifferent product characteristics from each other to calculate anaverage fault ratio θ of chips in circuit patters in upper wiring layers(Step 246).

The average fault ratio calculation processing part derives an averagefault ratio prediction model having a wiring area S_(L) as anexplanatory factor to determine model coefficients C4 and C5 (Step 247).

The average fault ratio calculation processing part stores an averagefault ratio prediction model

θ×S=C4×S _(L) +C5  (Eq. 4)

for circuit patterns of the upper wiring layers into the average faultratio prediction model database (Step 248).

Now, details will be described.

FIG. 31 shows an example of the average fault ratio prediction modeldatabase 202. As shown in the figure, the average fault ratio predictionmodel database 202 registers, for each layer name 2021, a circuitpattern 2022 affected by a defect detected in that layer and an averagefault ratio prediction model 2023.

A circuit pattern 2022 is a pattern stacked on a silicon wafer in thecourse of manufacturing a gate array product, and corresponds to a masklayout pattern. In the example of FIG. 31, layers are classified intotransistor formation layers (L and FG) in which individual gate modulesare formed and wiring layers in which SRAMs are formed. The wiringlayers are further classified into a lower layer (M1), an intermediatelayer (M2) and an upper layer (M3).

An average fault ratio prediction model 2023 is obtained for eachcircuit pattern 2022 as described in the following.

A critical area of a chip, which is a product of the average fault ratioθ of the chip and the chip area S, is expressed as a sum of criticalareas of elements constituting the chip. Among the elements constitutinga chip, those that are connected and affect yield of the chip are anSRAM part and a Logic part.

For example, in the case of a product that comprises a SRAM part, aLogic part and another part, the critical area θ*S of a chip isexpressed by the following formula

θ*S=θ _(SRAM) *S _(SRAM)+θ_(Logic) *S _(Logic)+θ_(Other) *S_(Other)  (Eq. 5)

by using the average fault ratio θ_(SRAM) of the SRAM part, the areaS_(SRAM) of the SRAM part, the average fault ratio θ_(Logic) of theLogic part, the area S_(Logic) of the Logic part, the average faultratio θ_(Other) of the other part and the area S_(Other) of the otherpart.

Here, the part other than the SRAM part and the Logic part does notaffect yield of a chip as described above even if a circuit pattern isformed from the viewpoint of layout, and thus is an area for which thekill ratio becomes zero. Accordingly, the third term on the right sideof Eq. 5 is deleted, and the average fault ratio prediction model isexpressed by the following formula.

θ*S=θ _(SRAM) *S _(SRAM)+θ_(Logic) *S _(Logic)  (Eq. 6)

In the circuit patterns (L, FG) of the transistor formation layers whereindividual gate modules are formed and the circuit pattern (M1) of thelower wiring layer where gate modules are wired to form an SRAM, onlythe SRAM part and the Logic part affect the yield, and the other partdoes not affect the yield. Accordingly, in these circuit patterns 2022,the average fault ratio prediction model expressed by (Eq. 6)constructed only by the sum of the critical areas of the SRAM part andthe Logic part can be used as it is. Thus, the average fault ratiocalculation processing part stores the above formula (Eq. 6) as theaverage fault ratio prediction models 2023 for these circuit patterns2022. The average fault ratio θ_(SRAM) of the SRAM part and the averagefault ratio θ_(Logic) of the Logic part can be obtained by thebelow-described Critical Area Analysis (CAA) simulation.

On the other hand, in the circuit pattern (M2) of the intermediatewiring layer, wiring for connecting adjacent circuit blocks and wiringfor leading in electrical signals from upper wiring layer are formed.Accordingly, a part other than the SRAM part and the Logic part is alsowired, and this affects the yield. Thus, it is not possible to derive anaverage fault ratio prediction model 2023 only by the sum of thecritical areas of the SRAM part and the Logic part as in the case of thelower wiring layer. Thus, several varieties (for example, fivevarieties) having different feature quantities are selected from thegroup of products that are manufactured by process similar to theprocess for the product A, and the below-described CAA simulation isperformed for each of the selected varieties to calculate an averagefault ratio θ of a chip as a whole. Then, the regression analysis isperformed to derive an average fault ratio prediction model 2023 havingthe SRAM area and the Logic area as explanatory factors.

In detail, regression analysis is performed using the product(corresponding to output Y) of the average fault ratio θ of a chip,which have been obtained from the selected five varieties of products,and the chip area S, and the SRAM part area and the Logic part area(corresponding to input X) among the feature quantities of the selectedfive varieties of products, to calculates model coefficients C1 and C2for the SRAM part area and the Logic part area and a constant C3.

Here, the derived average fault ratio prediction model 2023 is shown as(Eq. 7).

θ*S=C1*S _(SRAM) +C2*S _(Logic) +C3  (Eq. 7)

The average fault ratio calculation processing part stores (Eq. 7) asthe average fault ratio prediction model 2023 for the circuit pattern(M2) of the intermediate wiring layer.

FIG. 32 shows an example of distribution of product characteristics offamily products manufactured by a process similar to the process for theproduct A. To derive the average fault ratio prediction model 2023 forthe circuit pattern of the intermediate wiring layer, a predeterminednumber of products are selected from this group of products.

Further, the circuit pattern (M3) in the upper wiring layer is one forforming wiring that receives and delivers electrical signals betweencircuit blocks arranged over the chip, and thus wiring length is long.Thus, similarly to the case of the intermediate wiring layer, varieties(for example, five varieties) having different feature quantities areselected, and the below-described CAA simulation is performed for eachof the selected varieties to calculate the average fault ratio θ of achip. Then, the regression analysis is performed to derive an averagefault ratio prediction model 2023 having the wiring area S_(L) as anexplanatory factor.

In detail, the regression analysis is performed using the product(corresponding to output Y) of the average fault ratio θ of a chip,which has been obtained from five varieties of products, and a chip areaS, and a wiring area (corresponding to input X) among productcharacteristics of the five varieties of products, to determined a modelcoefficient C4 for the wiring area and a constant C5.

The derived average fault ratio prediction model 2023 is shown as (Eq.8)

θ*S=C4*S _(L) +C5  (Eq. 8)

The average fault ratio calculation processing part stores (Eq. 8) asthe average fault ratio prediction model 2023 for the circuit pattern(M3) of the upper wiring layer.

As described above, the average fault ratio calculation processing partgenerates an average fault ratio prediction model 2023 for each layer,completes the average fault ratio prediction model database 202, andstores the database 202 into the storage 200.

In the above processing, the average fault ratio calculation processingpart performs the CAA simulation using the conventional Critical AreaAnalysis with respect to a chip as a whole, the SRAM part or the Logicpart as the target of the simulation to obtain the average fault ratio θof a chip as a whole, the average fault ratio θ_(SRAM) of the SRAM partor the average fault ratio θ_(Logic) of the Logic part. This CAAsimulation or the Critical Area Analysis is a well-known method, andthus its procedure will be described here simply. FIG. 33 is a diagramfor explaining a procedure for obtaining an average fault ratio by theCritical Area Analysis.

The Critical Area Analysis comprises a step (FIG. 33( a)) in whichlayout data of a circuit pattern are inputted to generate a curve 41 offailure probability against defect diameter, and a step (FIG. 33( b)) inwhich an inspection result of a manufacturing line is inputted togenerate a defect occurrence rate curve (the normalized defect sizedistribution function curve) 42 or a defect particle diameterdistribution curve is generated by using a formula. Then, by obtainingthe hatched part 43 from a product sum of these two curves 41 and 42(FIG. 33( c)), an average fault ratio 0 is obtained.

The curve 41 of FIG. 33( a) shows that the larger the diameter of defectis, the higher the probability of occurrence of failure (short circuitor breaking) in a circuit pattern. Further, it is known that defectsoccurring in a manufacturing line are expressed byF(x)=(n−1)·xo^(n−1)·x^(−n), where F(x) is occurrence rate, x is adiameter of a defect, and n is a defect size distribution parameter. Thecurve 42 in FIG. 33( b) is depicted according to this formula. Theproduct of the curve 41 and the curve 42 is obtained, and then theintegral of the product from the minimum diameter xo to infinity leadsto the area of the hatched part 43 of FIG. 33( c). By this, it ispossible to obtain a electric fault ratio θA of the layer c of theproduct A, for example.

After the processing of Step 141, the average fault ratio calculationprocessing part calculates areas of the SRAM part and the Logic part byusing the chip size of the product A, the occupancies of the SRAM partand the Logic part, which have been previously acquired by the productcharacteristic acquisition processing part. Then, the acquired θ_(SRAM)and θ_(Logic) of the SRAM part and the Logic part and the respectiveareas are substituted into the average fault ratio prediction model 2023for the circuit pattern 2022 associated with the layer c 2021 stored inthe memory 28, to calculate the average fault ratio θ_(A) of the layer cof the product A. The calculated average fault ratio θ_(A) is storedinto the memory 28. Also, as for the product B, the average fault ratioθ_(B) of the layer c is calculated similarly by using the productcharacteristics of the product B, which have been previously acquired bythe product characteristic acquisition processing part. The calculatedaverage fault ratio θ_(B) is stored into the memory 28 (Step 142). Theaverage fault ratio prediction model database can be used for all theaverage fault ratio calculation processing, and thus it is sufficient toperform the average fault ratio prediction model generation processingonce before the average fault ratio calculation processing.

Next, prediction target product monthly electric fault densitycalculation processing (Step 18 of FIG. 19) performed by the predictiontarget product monthly electric fault density calculation processingpart will be described. The electric fault density of the product can beobtained by Doc×θo from the total defect density Doc of the layer c andthe average fault ratio θo of the layer c. FIG. 34 shows flow of theprediction target product monthly electric fault density calculationprocessing of the present embodiment.

The prediction target product monthly electric fault density calculationprocessing part acquires the monthly electric fault density D_(AC) ofthe layer c of the product A from the monthly electric fault densitymanagement table 204 for the product A, and stores the acquired monthlyelectric fault density D_(AC) into the memory 28 (Step 161).

Here, the electric fault density of the product B is calculated asfollows.

Electric  fault  density  of  the  layer  c  of  the  product  B = D_(OC) * θ_(B) = D_(OC) * θ_(A) * θ_(B)/θ_(A)

where D_(OC) is the total defect density of the defects occurring in thelayer c. Here, D_(OC)*θ_(A) corresponds to the monthly electric faultdensity D_(AC) of the product A. Thus, the electric fault density of theproduct B can be expressed as follows.

Electric  fault  density  of  the  layer  c  of  the  product  B = electric  fault  density  of  the  layer  c  of  the  product  A * θ_(B)/θ_(A) = D_(AC) * θ_(B)/θ_(A)

The prediction target product monthly electric fault density calculationprocessing part calculates the monthly electric fault density D_(BC) ofthe layer c of the product B from the ratio (θB/θA) of the average faultratio θB of the layer c of the product B to the average fault ratio θAof the layer c of the product A and the monthly electric fault densityD_(AC) of the layer c of the product A. The average fault ratios havebeen calculated by the average fault ratio calculation part. Here,D_(BC)=D_(AC)*(θ_(B)/θ_(A)) is calculated, and the result is stored intothe memory 28 (Step 162).

Next, manufacturing history acquisition processing (Step 19 of FIG. 19)performed by the manufacturing history acquisition processing part willbe described. FIG. 35 shows a flow of the manufacturing historyacquisition processing of the present embodiment.

As described above, the manufacturing history acquisition processingpart receives designation of the manufacturing history of the lot B1 ofthe yield prediction target product B from the operator through the datainput part 26, and stores the manufacturing history instructed into thememory 28 (Step 171). The manufacturing history acquisition processingcan be performed at any time before yield calculation processing.

Next, the yield calculation processing (Step 20 of FIG. 19) performed bythe yield calculation processing part will be described. FIG. 36 shows aflow of the yield calculation processing of the present embodiment.

The yield calculation processing part identifies the date at which theprocessing of the layer c of the lot B1 of the product B was performed,on the basis of the month of the launch of transistor formation layer orthe month of the launch of wiring layer and the expected month ofelectrical inspection, which have been acquired by the manufacturinghistory acquisition calculation processing part. Then, the electricfault density D_(BC) of the identified month is read from the monthlyfatal density of the layer c of the product B, which has been calculatedby the prediction target product monthly electric fault densitycalculation processing part. Then, the electric fault density D_(BC) isstored into the memory 28 (Step 181).

Here, an example of method of estimating the date at which theprocessing of the layer as the yield prediction target was performedwill be described.

In the case of a manufacturing process in which the yield predictiontarget layer belongs to transistor formation layers, estimation anddetermination are made assuming that the processing of the transistorformation layers is finished in two months from the month of the launchof the transistor formation layers. FIG. 37 is a diagram explaining aprocedure in which the date of performing the processing is estimated onthe basis of the inputted launch month and the electric fault density isacquired from the table storing the monthly electric fault density ofeach layer of the product B, in the case of the process whose yieldprediction target layer belongs to the transistor formation layers.Here, for example, the method of estimation of the processing date ofeach layer will be described, assuming that the layers a through cbelong to the transistor formation layers. Referring to the figure, inthe case where the month of the launch of the transistor formationlayers is January, it is possible to judge that the three layers a, band c have been processed between January and February since theprocessing of the transistor formation layers requires two months.Assuming that the processing of each layer is performed at a constantspeed, it is possible to estimate that the layer a was processed inJanuary, the layer b from January to February, and the layer c inFebruary. According to the example of the figure, the electric faultdensity D_(Ba) of the layer a is 0.091, the monthly electric faultdensity DBb of the layer b is 0.027 as an approximation using theaverage of the monthly electric fault densities of January and February,and the electric fault density D_(Bc) of the layer c is 0.054.

Further, in the case where the yield prediction target layer belongs towiring layers, the processing date of the yield prediction target layeris estimated assuming that the layer is processed at a constant speedbetween the month of the launch of the wiring layers and the expectedmonth for electrical inspection. FIG. 38 is a diagram for explaining aprocedure in which the date of performing the processing is estimated onthe basis of the inputted launch month and the electric fault density isacquired from the table storing the monthly electric fault density ofeach layer of the product B, in the case of the process whose yieldprediction target layer belongs to the wiring layers. Here, for example,it is assumed that the layers d to f belong to the wiring layers. Asshown in the figure, in the case where the month of the launch of thewiring layers is May and the expected month for electrical inspection isJuly, the layers d to f are processed for three months from May to July.Since the manufacturing is assumed to be performed at a constant speed,it is estimated that the layer d is processed in May, the layer e inJune, and the layer f in July respectively. To acquire the electricfault density of the layer f for example, the electric fault density ofJuly is required. Since the fatal defect density of July, i.e., theexpected month for electrical inspection, has not been acquired yet, theelectric fault density of June is substituted for the electric faultdensity of July.

After Step 181, the yield calculation processing part calculates Eq. 9by using the electric fault density D_(BC) stored in the memory 28 inStep 181 and the chip area S_(B), and calculates the predicted yieldY_(BC) for the layer c of the lot B1 by the following formula.

Y _(BC)=exp(−D _(BC) *S _(B))  (Eq. 9)

The calculated predicted yield is expressed in percent terms and theresult is stored into the memory 28 (Step 182). Here, the chip areaS_(B) is calculated by using the chip size in the product characteristicmanagement table 201.

For example, assuming that the layer c of the lot B1 has been processedin February as shown in FIG. 37, the monthly electric fault densityD_(BC) is 0.054. Further, according to the product characteristicmanagement table 201 of FIG. 28, the chip size of the product B is 1.6cm. Thus, in this example, the predicted yield Y_(BC) of the layer c ofthe lot B1 of the product B is calculated asY_(Bc)=exp(−0.054*1.6*1.6)=087. The predicted yield Y_(Bc) is obtainedas 87%, and this result is stored into the memory 28.

Thereafter, the yield calculation processing part reads the yieldprediction result Y_(Bc) stored in the memory 28 and outputs the resultthrough the data output part 27 (Step 183).

Hereinabove, the case of predicting the yield of one layer c of apredetermined lot B1 of the product B has been described as an example.To predict the yield Y of the product B as a whole, the yield of eachlayer is calculated by a similar procedure, to obtain the product of thecalculated yields as yield Y.

In the above embodiment, the yield of each layer is obtained and theyield Y of the product B as a whole is obtained by multiplying therespective yields of the layers. However, a procedure for obtaining theyield Y of the product B as a whole is not limited to this. The yield Yof the product B as a whole can be calculated by obtaining respectiveelectric fault densities D_(Ba), D_(Bb), D_(Bc), D_(Bd), . . . for thecircuit layers a, b, c, d, . . . constituting the product B by aprocedure similar to the above embodiment and then by calculatingY=exp(−(D_(Ba)+D_(Bb)+D_(Bc)+D_(Bd)+ . . . )×S_(B)). Here, S_(B) is thechip area of the product B.

FIG. 39 is a diagram for explaining a procedure in which the processingmonth is estimated and the electric fault density is obtained from thetable storing the monthly electric fault density of each layer of theproduct B, to calculate the yield. For example, the case of a lot forwhich the month of launch of the transistor formation layers is January,the month of launch of the wiring layers is May, and the expected monthfor electrical inspection is July is considered. Then, assuming that thetransistor formation layers (the layers a-c) have been processed in twomonths, the respective electric fault densities of the layers arecalculated as D_(Ba)=0.091, D_(Bb)=(0.026+0.028)/2=0.027, andD_(Bc)=0.054. The electric fault densities of the wiring layers (thelayers d-f) are D_(Bd)=0.034, D_(Be)=0.008, and D_(Bf)=0.009. The totalsum of the electric fault densities of the layers a-f is 0.223, and theyield Y of the lot is calculated as 56% in this case.

FIG. 40 shows transition of the electric fault density of eachtransistor formation layer, which has been calculated with respect to 18lots. It is found that the electric fault density of the layer afluctuates largely. As a result, it is possible to judge thatdifferences in the electric fault densities of the transistor formationlayers are caused mainly by the layer a.

FIG. 41 shows a result of comparison between the predicted values of thefinal yield, which have been predicted by applying the yield predictionsystem of the present embodiment to 18 lots, and theactually-measurement values. The line connecting black quadrangles showsthe predicted values, and the line connecting white quadrangles showsthe actually-measured values. As shown in the figure, although there aretwo lots whose yields fall largely owing not only to functional failurescaused by defects but also to characteristic defects, the other lotsshow favorable prediction results. Thus, the present embodiment canpredict the yield that reflects fluctuation in defects occurring in eachlayer, by calculating the electric fault density of each layer.

According to the present embodiment, it is possible, givingconsideration to un-connected gate modules, to calculate an averagefault ratio, by employing an average fault ratio prediction model thatuses product characteristics. As a result, in particular, accuracy ofyield prediction of transistor formation layers is improved. When theyield can be predicted accurately in the stage where transistorformation layers have been made, it is possible to select products thatcan be processed using such master wafers. For example, a product whosetransistor formation layers have good yield can be used for producing adifficult product whose wiring layers have a high average fault ratio.Or, a product whose transistor formation layers have poor yield can beused for producing easily-producible product whose wiring layers have alow average fault ratio.

As described above, the yield prediction system of the presentembodiment can predict the average fault ratio of the yield predictiontarget product B conveniently from the product characteristics, and canpredict the yield Y_(B) of the product B, which reflects transition ofthe electric fault density of each layer in the manufacturing line. Inother words, in the course of manufacturing a wide variety of electronicdevices that are manufactured in small volumes by utilizing existingcircuits on a substrate of, for example, a gate array product, it ispossible to predict the yield of a prescribed layer accurately. Owing toaccurate yield prediction in the course of manufacturing, themanufacturer can easily make a manufacturing plan for the subsequentperiod. For example, in the case where a resultant yield is lower than adesired yield, an additional lot can be launched without awaitingcompletion of the product. In the reverse case, another productdifferent in wiring layers may be manufactured. Thus, a requiredquantity of product can be manufactured to meet the delivery deadline bylaunching an additional lot without awaiting completion of product,preventing delivery delay. Further, manufacturing of surplus productscan be prevented by manufacturing another product having differentwiring layers, and the product B can be manufactured at low cost. Thus,according to the present embodiment, it is possible to improve theaccuracy of yield prediction made in the course of manufacturing of aproduct, and thus the probability of attaining the desired yield of thetarget product is raised. As the probability of attaining the desiredyield becomes higher, the possibility of wasteful manufacturing islowered, and the possibility of manufacturing the product at low costbecomes higher.

Further, according to the present embodiment, an average fault ratio canbe calculated conveniently by using product characteristics as describedabove. As a result, calculation time can be shortened.

As described above, according to the present embodiment, it is possibleto make dynamic yield prediction that reflects the number of dustparticles occurring in the manufacturing process of circuit layers, andthe yield prediction accuracy is improved.

Although the above embodiment considers failure probability owing todefects only on the basis of diameters of the defects, the embodiment isnot limited to this. For example, an average fault ratio predictionmodel may be derived based on a failure probability calculation resultthat considers up to remedy allowing for potential of a circuit pattern.

1. An electronic device yield prediction system for predictingmanufacturing yield of an electronic device, wherein: the electronicdevice yield prediction system comprises: a defect density calculationunit, which calculates total number of defects occurring in amanufacturing line; a critical area calculation unit, which calculates acritical area; and a yield calculation unit, which calculates themanufacturing yield by using defect density of the manufacturing line,which has been calculated by the defect density calculation unit, and acritical area of the electronic device, which has been calculated by thecritical area calculation unit; and wherein the critical areacalculation unit uses a critical area prediction model that calculates acritical area from product characteristics, which are factorscharacterizing the electronic device.
 2. An electronic device yieldprediction system of claim 1, wherein: the product characteristicsinclude at least one of a chip size, an inner area size excluding aperipheral I/O part, kinds of mounted macro-cells, numbers of mountedmacro-cells, a basic cell employment ratio, an I/O cell height, and amask area ratio.
 3. An electronic device yield prediction method forpredicting manufacturing yield of an electronic device, wherein: theelectronic device yield prediction method comprises: a defect densitycalculation step, in which total number of defects occurring in amanufacturing line is calculated; a critical area calculation step, inwhich a critical area is calculated; and a yield calculation step, inwhich the manufacturing yield is calculated by using defect density ofthe manufacturing line, which has been calculated in the defect densitycalculation step, and a critical area of the electronic device, whichhas been calculated in the critical area calculation step; and in thecritical area calculation step, a critical area prediction model thatcalculates a critical area from product characteristics, which arefactors characterizing the electronic device, is used.
 4. A programproduct for making a computer function as: a defect density calculationunit, which calculates total number of defects occurring in amanufacturing line; a critical area calculation unit, which calculates acritical area; and a yield calculation unit, which calculates themanufacturing yield by using defect density of the manufacturing line,which has been calculated by the defect density calculation unit, and acritical area of the electronic device, which has been calculated by thecritical area calculation unit.
 5. An electronic device yield predictionsystem for predicting manufacturing yield of a first electronic device,wherein: the electronic device yield prediction system comprises: aelectric fault density calculation unit, which calculates, at apredetermined unit of time, electric fault density, which is density ofelectric faults causing failure among defects occurring inmanufacturing, by using actually measured data, with respect to a secondelectronic device whose wiring pattern is different from the firstelectronic device; an average fault ratio calculation unit, whichcalculates a first average fault ratio that indicates a ratio of defectscausing the first electronic device to be failure and a second averagefault ratio that indicates a ratio of defects causing the second deviceto be failure among defects occurring in manufacturing; a electric faultdensity translation unit, which calculates a electric fault density ofthe first electronic device by multiplying the electric fault density ofthe second electronic device, which has been calculated by the electricfault density calculation unit, by a ratio of the first average faultratio to the second average fault ratio, with the first and secondaverage fault ratio being calculated by the average fault ratiocalculation unit; and a yield calculation unit, which selects, on abasis of manufacturing history of a prediction target lot of a yieldprediction target product, electric fault density of a period in whichthe prediction target lot was processed, among electric fault densitiescalculated for the predetermined unit of time and recorded by theelectric fault density calculation unit, and uses the selected electricfault density to calculate the manufacturing yield; and wherein theaverage fault ratio calculation unit uses an average fault ratioprediction model that calculates an average fault ratio by using productcharacteristics, which are factors characterizing the first and secondelectronic devices.
 6. An electronic device yield prediction system ofclaim 5, wherein: the product characteristics include at least one of achip size, occupancy of functional blocks, and occupancy of a wiringarea.
 7. An electronic device yield prediction system of claim 5,wherein: the first electronic device has a plurality of circuit layers;the second electronic device has layers corresponding respectively tothe plurality of circuit layers of the first electronic device; theelectric fault density calculation unit, the average fault ratiocalculation unit, the electric fault density translation unit, and theyield calculation unit calculate respectively the electric fault densityof the second electronic device, the first average fault ratio, thesecond average fault ratio, and the electric fault density of the firstelectronic device, for each of the circuit layers of the firstelectronic device and the circuit layers of the second electronic devicecorresponding respectively to the circuit layers of the first electronicdevice; and wherein based on the manufacturing history, the yieldcalculation unit selects, for each of the circuit layers, electric faultdensity of a period in which the prediction target lot was processedamong electric fault densities calculated and recorded by the electricfault density calculation unit, and uses a sum of the selected electricfault densities for the circuit layers to calculate the yield of thefirst electronic device as a whole.
 8. An electronic device yieldprediction method for predicting a manufacturing yield of a firstelectronic device, the method comprising: a electric fault densitycalculation step, in which electric fault density, which is density ofdefects causing failure among defects occurring in manufacturing, iscalculated, at a predetermined unit of time, by using actually measureddata, with respect to a second electronic device whose wiring patternsare different from the first electronic device an average fault ratiocalculation step, in which a first average fault ratio that indicates aratio of defects causing the first electronic device to be failure and asecond average fault ratio that indicates a ratio of defects causing thesecond device to be defective among defects occurring in manufacturing,are calculated; a electric fault density translation step, in whichelectric fault density of the first electronic device is calculated bymultiplying the electric fault density of the second electronic device,which has been calculated in the electric fault density calculationstep, by a ratio of the first average fault ratio to the second averagefault ratio, with the first and second average fault ratio beingcalculated in the average fault ratio calculation step; and a yieldcalculation step, in which based on manufacturing history of aprediction target lot of a yield prediction target product, electricfault density of a period in which the prediction target lot wasprocessed is selected among electric fault densities calculated for thepredetermined unit of time and recorded in the electric fault densitycalculation step, and uses the selected electric fault density tocalculate the manufacturing yield; and in the average fault ratiocalculation step, an average fault ratio prediction model thatcalculates an average fault ratio by using product characteristics,which are factors characterizing the first and second electronicdevices, is used.
 9. An electronic device yield prediction method ofclaim 8, wherein: the first electronic device has a plurality of circuitlayers; the second electronic device has layers correspondingrespectively to the plurality of circuit layers of the first electronicdevice; and the electric fault density calculation step, the averagefault ratio calculation step, and the electric fault density translationstep are performed for each of the circuit layers of the firstelectronic device and the circuit layers of the second electronic devicecorresponding respectively to the circuit layers of the first electronicdevice, to calculate electric fault density of the circuit layer inquestion, of the first electronic device, and the yield of the firstelectronic device as a whole is obtained by taking a sum of therespective electric fault densities of the circuit layers.
 10. A programproduct for making a computer function as: a electric fault densitycalculation unit, which calculates, at a predetermined unit of time,electric fault density, which is a density of defects causing failureamong defects occurring in manufacturing, by using actually measureddata, with respect to a second electronic device whose wiring pattern isdifferent from a first electronic device, which is a target ofprediction of manufacturing yield; an average fault ratio calculationunit, which calculates a first average fault ratio that indicates aratio of defects causing the first electronic device to be failure and asecond average fault ratio that indicates a ratio of defects causing thesecond device to be failure among defects occurring in manufacturing,according to an average fault ratio prediction model that uses productcharacteristics, which are factors characterizing the first electronicdevice and the second electronic device; a electric fault densitytranslation unit, which calculates a electric fault density of the firstelectronic device by multiplying the electric fault density of thesecond electronic device, which has been calculated by the electricfault density calculation unit, by a ratio of the first average faultratio to the second average fault ratio, with the first and secondaverage fault ratio being calculated by the average fault ratiocalculation unit; and a yield calculation unit, which selects, on abasis of a manufacturing history of a prediction target lot of a yieldprediction target product, electric fault density of a period in whichthe prediction target lot was processed, among electric fault densitiescalculated for the predetermined unit of time and recorded by theelectric fault density calculation unit, and uses the selected electricfault density to calculate the manufacturing yield.